FIG. 37 shows an example of a conventional chip resistor (see Japanese Unexamined Patent Application Publication 2002-57009, for example). A chip resistor B shown in the drawing is constituted such that a pair of electrodes 91 is provided on a lower surface 90b of a metallic chip-form resistor 90. The electrodes 91 are separated from each other by a void portion 93. A solder layer 92 is formed on the lower surface of each electrode 91 as means for improving solder ability during mounting.
This chip resistor B is manufactured using a method such as that shown in FIGS. 38A to 38E. First, as shown in FIG. 38A, two metallic plates 90′, 91′ are prepared as the materials for the resistor 90 and electrodes 91, and then, as shown in FIG. 38B, the metallic plate 91′ is superposed on the lower surface of the metallic plate 90′ and joined thereto. Next, as shown in FIG. 38C, a part of the metallic plate 91′ is cutaway by machining to form the void portion 93. Next, as shown in FIG. 38D, a solder layer 92′ is formed on the lower surface of the metallic plate 91′, and then the metallic plates 90′, 91′ are cut as shown in FIG. 38E. Thus the chip resistor B is manufactured.
However, this prior art has the following problems.
Firstly, the region between the pair of electrodes 91 on the lower surface 90b of the resistor 90 and each side face 90c of the resistor 90 are not protected by insulation. As a result, when the chip resistor B is surface-mounted in a desired location using solder, a part of the solder may seep out from below the electrodes 91 and become adhered to the lower surface 90b of the resistor 90 or the side faces 90c. When such a situation arises, a large error occurs in the resistance value, leading to aberrations in the specifications of electric circuits produced using the chip resistor B. As the resistance value of the chip resistor B decreases such that the need to reduce the error in the resistance value increases, this problem becomes more serious.
Secondly, the series of manufacturing operations in the manufacturing method of this prior art is complicated, and hence the productivity of the chip resistor is poor. More specifically, in the prior art, the void portion 93 is formed by machining. Further, during this machining process, a dimension Sb between the pair of electrodes 91 must be set precisely. Accordingly, this machining process must be performed meticulously, leading to a deterioration in the productivity of the chip resistor B. Also in this prior art, the chip resistor B is manufactured through a cutting process, and errors may occur in the resistance values of the electrodes depending on the precision of this cutting process.
Thirdly, when the chip resistor is incorporated into a desired circuit, an inspection is performed to determine whether or not the chip resistor has been mounted appropriately. In this case, the determination as to whether or not the chip resistor has been soldered appropriately is preferably performed by means of exterior observation. For this purpose, it is desirable that a part of the solder used in the mounting operation be formed as a solder fillet adhered to the end face of the resistor in the chip resistor. In so doing, it is possible to determine with a high degree of likelihood that the chip resistor has been mounted appropriately by confirming the existence of the solder fillet, and conversely, that the chip resistor has been mounted inappropriately when the solder fillet cannot be confirmed. In the prior art, however, although the solder layer 92 is formed on the lower surface of each electrode 91, it is sometimes difficult to form a solder fillet merely by providing the solder layer 92. When the chip resistor B is surface mounted in a desired location using a solder reflow method, the parts of the electrodes 91 to be joined are coated in advance with cream solder, but if the coating amount is insufficient, an appropriate solder fillet is not formed. Hence in the prior art, it is difficult to determine whether or not the chip resistor B has been surface mounted appropriately according to the presence of a solder fillet, which is inconvenient. Furthermore, since a solder fillet is not formed in the prior art, the joining strength of the solder may not be sufficient.
Fourthly, the chip resistor B is constituted such that a width Sa of each electrode 91 in the arrangement direction of the electrode pair 91 is comparatively large. Hence, when a measurement probe is brought into contact with the electrode pair 91 to measure the resistance values thereof, a large difference occurs between a resistance value Ra when the measurement probe contacts an inside edge portion 91a of the respective electrodes 91, and a resistance value Rb when the measurement probe contacts an outside edge portion 91b. This large difference in the resistance value according to the part of the electrodes 91 contacted by the measurement probe is undesirable since it leads to a wide variation in the resistance value of the chip resistor B depending on the manner in which the chip resistor B is used. More specifically, when the chip resistor B is surface mounted in a desired location using solder, for example, the solder may deviate toward the inside edge portion 91a of the electrodes 91, for example, rather than adhering tightly to the entire lower surface of the electrodes 91. Conversely, the solder may deviate toward the outside edge portion 91b of the lower surface of the electrodes 91. In the prior art, wide variation in the resistance value occurs in such cases. When the chip resistor B has a low resistance of 10 mΩ or less, for example, the difference between the aforementioned resistance value Ra and resistance value Rb is small, but compared to the overall resistance value of the chip resistor B, this difference is proportionately extremely large. Therefore, this problem becomes more serious as the resistance of the chip resistor B decreases.
As means of suppressing the fourth problem described above, the thickness of the electrodes 91 may be increased so that the electrical resistance of the electrodes 91 themselves is reduced, for example. However, when such means are employed, the overall thickness of the chip resistor B increases, the amount of the metallic plate 91′ that must be cut to form the void portion 93 increases, and as a result, the manufacturing cost of the chip resistor B rises.